1. Field of the Invention
The present invention generally relates to block compiler systems and, more particularly, to block compiler systems for generating memory structures in application-specific integrated circuits.
2. State of the Art
It is known to use computerized block compiler systems for custom designing application-specific integrated circuits (ASICs). Block compiler systems can, for instance, allow circuit design engineers to design ASICs by drawing upon libraries containing various designs of sub-cells that can be assembled to generate higher level cells. ASICs normally include one or more functional blocks, or cells which can be classified individually as LSI or VLSI circuits. For instance, a cell within an ASIC device can be a read-only memory (ROM), a random access memory (RAM), or an arithmetic logic unit.
In practice, it is important that block compiler systems allow design engineers a high degree of flexibility in choosing cell configurations. In response to this need, some block compiler systems allow users the ability to specify memory structures in terms of depth (i.e., the number of words contained in the memory) and word length (i.e., the number of bits per word). Conventional compiler systems, however, usually structure memories by rows and columns in patterns which are fixed according to the specified memory size and, therefore, do not allow users to specify the internal structure of compiled memories.
In the cell-based compiler system known as the CROM01 compiler system available from VLSI Technology, Inc., of San Jose, Calif., users are provided with limited choices as to internal structures of compiled memories. More particularly, the CROM01 compiler system allows a user to specify the internal structure of a given size ASIC memory only in terms of the memory containing either three or four column address lines.
There are several advantages to block compiler systems providing the capability of choosing internal memory structures for compiled memories and, in particular, for ASICs that are based upon gate arrays. One reason relates to the fact that bases for gate array circuits are normally available only in fixed sizes. Thus, a given gate array base may not accommodate a memory structure that is physically long and narrow even though the base has sufficient gates, in total, to implement the memory; accordingly, the long and narrow memory structure would have to be placed on a larger (and more expensive) gate array base. On the other hand, a physically more square structure of the memory might be fitted upon a smaller gate array base even if the memory occupies more gate sites. (Because of trade-offs in internal buffering and peripheral logic configurations, internal structure can affect the overall area of a memory, in terms of gate sites, even if the total words of the memory is fixed.)
Another reason that circuit design engineers would benefit from having the capability of choosing internal memory structures when using block compiler systems is that memory access times may vary according to the structure of the memories. In other words, internal memory structure, as well as internal buffering and peripheral logic, can affect the access times of memories.